1. Field of the Invention
The present invention relates to a large scale semiconductor memory device with high reliability.
2. Description of the Related Art
Semiconductor memories are broadly classified as RAMs (Random Access Memory) and ROMs (Read-only Memory). Among them, dynamic RAMs (DRAMs) are most commonly used as main storages for computers. A memory cell which stores memory is constituted with a storage capacitor and a transistor to read the charge stored in the capacitor. The memory can be realized with the minimum constituent elements as a RAM, so that it can suitably form a large scale storage unit. Consequently DRAMs are relatively inexpensive and have been manufactured in large quantities.
However, a problem with the DRAM is that it is apt to be unstable. The primary factor of instability is that the memory cell itself has no amplification activity, so that the read out signal voltage from the memory cell is small. Therefore, its action can easily be influenced by various kinds of noises. Further, a RAM can be divested of information charge accumulated in a capacitor by a p-n junction current (leak current) existing in a memory cell. Therefore, before the charge disappears, the memory cell is forced to perform refresh operations (refresh write) periodically in order to maintain stored information. The time period is called a refresh time and it is in the order of 100 msec. at present. However, this time period needs to be lengthened with the increase in storage capacity. In other words, there is a need to control the leak current; however this is getting more and more difficult with the miniaturization of the element.
The memory that solves this problem is a ROM, in particular a flash memory. The flash memory is, as generally known, as small as or smaller than the DRAM cell and it has a gain inside the memory cell, so that its signal voltage is essentially large; therefore, the action of the flash memory is stable. Since the flash memory stores storage charge in a storage node enveloped with an insulating film, the write time is extremely long.
When writing is repeated, the insulating film is forced to pass a current, and the insulating film gradually deteriorated and at least it becomes a conductive film, which makes it impossible to hold the charge. Therefore, the number or write times is generally limited to be within 100,000 times. In other words, the flash memory cannot be used as RAM. As explained in the above, both DRAMs and flash memories are appropriate for a large capacity memory, but each of them has advantages and disadvantages; therefore, the present invention attempts to utilize the advantages of both of them.
An object of the present invention is to provide a small-sized memory cell having gain inside and being able to operate as a RAM, a semiconductor memory device using the above cells and a manufacturing method for the memory device or its manufacturing apparatus. Further, another object of the present invention is to provide a nonvolatile RAM having the possibility to be able to guarantee a holding time of the order of 10 years owing to the memory cell constitution having no p-n junction current in an accumulation (storage) node.
In order to solve the above-mentioned problem, the constitution of the memory cell provided by the present invention comprises a MOS transistor holding an information voltage corresponding to information in its gate, a write transistor for providing the information voltage, and a capacitor for controlling the gate voltage.
When the memory cells are constituted as a memory cell array, a first terminal and a second terminal of the write transistor are respectively connected to the gate and a data line to provide write data, a third terminal thereof is connected to a word line, and further an electrode at an end of the capacitor is connected to the gate, the voltage of an electrode at another end is controlled at the time of reading the memory cells. The electrode at another end of the capacitor is connected to the word line.
Because of the characteristics of the write transistor, the maximum width of a depletion layer in a channel portion is desirable to be larger than the gate interval of the write transistor. Concerning the channel length L of the write transistor, a desirable condition among a gate internal D, a thickness of the gate insulation film tg, a dielectric constant of silicon ∈si and the dielectric constant of the gate insulation film ∈g will be provided.
It is desirable to set the threshold value and the coupling capacity such that the write transistor is in an OFF state when not selected, and is in an ON state or in an OFF state according to a high state or a low state of the storage information at the time of reading.
As for a manufacturing apparatus to form the semiconductor device, it is desirable that the semiconductor films and the tunnel films are formed continuously and stably without touching the open air. More specifically, we can consider a constitution in which chambers for forming various kinds of films are connected to each other.
As a transistor provided by the present invention, there is provided a semiconductor device which is formed on a substrate, wherein the quantity of charge passing through the device can be controlled by controlling an electric field given thereto, comprising: a first node and a second node serving as a path of the charge; a channel region disposed between the first node and the second node and serving as the path of the charge; gate electrodes disposed for the purpose of providing the electric field to the channel region; a first tunnel barrier disposed between the first node and the channel region; and a second tunnel barrier disposed between the second node and the channel region; wherein the first node, the channel region, and the second node are formed with silicon as a main ingredient, and the impurity density of the first and the second nodes is higher than that of the channel portion, at least part of the tunnel barrier is formed with a nitride film or an oxide film, and the first node, the channel region, and the second node are stacked into a multi-layered structure in a direction having a right angle with that of the main surface of the substrate.
Owing to the fact that the path of the current is perpendicular to the surface of the substrate, a transistor can be constituted in a small area. As an example, the impurity density in the first node and the second node is 1020 cmxe2x88x923 or more and the impurity density in the channel space is 1017 cmxe2x88x923 or less. At least part of the tunnel barrier can be formed directly with a nitride film made by thermal nitrification.
Further, as a concrete device constitution, the first node, the channel region, and the second node are formed in a multi-layered structure and are built in a pillar structure in the direction perpendicular with that of the main surface of the substrate, the gate electrodes are formed along the side surface of the pillar structure and the first gate electrode region and the second electrode region have the pillar structure in between when viewed in a cross sectional view taken along a plane being perpendicular to the main surface of the substrate, and in the channel region the maximum value DL of the interval between the first gate electrode region and the second gate electrode region is smaller than the maximum width Xd of the depletion layer, on the condition that Xd=5(2kT∈/(exe2x80x2eNc) where k is Boltzman constant, T is an absolute temperature in the work environment of the semiconductor device, ∈ is a dielectric constant of silicon, e is an absolute value of an electron charge, and Nc is an impurity density in the channel region.
It is practical that the relation between the length L of the channel region and the maximum value DL of the gate interval lies in the range L greater than DL. It is also effective that the gate electrode is made of p-type silicon having a density higher than that of the channel space.
When the film itself forming the tunnel barrier is used as a diffusion barrier, the impurity density in the first node, that in the channel space and that in the second node can be varied discontinuously making the first and the second tunnel barriers borders.
In order to control the characteristics of the transistor, it is also possible to form a third tunnel barrier between the first and the second tunnel barriers.
As explained later with reference to FIG. 4, according to the present invention, there is provided a transistor comprising: a source region and a drain region; a channel region disposed between the source region and the drain region; gate electrodes disposed for the purpose of providing an electric field to the channel region; a first nitride film disposed between the source region and the channel region; and a second nitride film disposed between the drain region and the channel region; wherein the source region, the channel region, and the drain region are formed with semiconductors as a main ingredient and the density of impurities in the source region and the drain region is higher than that in the channel region, and the density of impurities in the source region, the channel region, and the drain region shows a discontinuous profile making the first nitride film and the second nitride film borders.
As the guidance in a case where one performs the device design of the transistor according to the present invention, there is provided a transistor comprising: a first electrode, a channel region, and a second electrode piled up in order to form a multi-layered structure upon a substrate; gate electrodes disposed adjacent to the channel region through an insulation film; a first intermediate film serving as a first tunnel barrier disposed between the first electrode and the channel region; and a second intermediate film serving as a second tunnel barrier disposed between the second electrode and the channel region; wherein the relation between the length L of the channel region and the maximum value W of the width of the channel region is kept under the condition of L greater than W.
More specifically the length L of the channel region is equal to the interval between the first intermediate film and the second intermediate film, and seen from a cross sectional view taken along a plane perpendicular to the piled up direction of the first electrode, the channel region and the second electrode, the gate electrodes are disposed in both sides of the channel region, and the maximum value W of the width of the channel region denotes the maximum value of the interval of gate electrodes disposed being separated from each other.
According to a manufacturing method provided by the present invention, there is provided a manufacturing method of a semiconductor device, comprising: a step of forming a plurality of polysilicon films and nitride films, in which each of them has different densities of impurities from each other and stacking them into a multi-layered structure in a state where the whole process is carried in an atmosphere being isolated from the open air, and a step in which the difference in the impurity densities between polysilicon films having different impurity densities can be reduced by thermal diffusion.
The details of the present invention will be made more clear by the following explanation.